1. Field of the Invention
The present invention relates to photolithography generally, and, in particular, to reticle structures for controlling resist profile slope.
2. Description of the Related Art
In many integrated circuit and nanostructure (e.g., MEMS device and magnetic disk head) manufacturing processes, it is desirable to produce features on the surface of the resulting device that are smoothed or tapered. For example, evaporated metal deposited over sharp topographical features, such as sharp-edged vias, generally do not deposit in a continuous film and might deposit too thinly at the edge of the via for reliable device operation. Where current densities are sufficiently high that electromigration of the metal can occur, the thin metal layer may retract over time until the metal is too thin to carry the current flowing therein, causing the device to fail before the design lifetime of the device. Even where electromigration is not an issue, the thinned metal layer can form cracks that make the manufactured device susceptible to moisture ingression, which might induce corrosion of the metal, reducing device reliability. The sharp features come about because resist patterns used to form the features underlying the metal, when viewed immediately after the resist is patterned and developed, often have near-vertical sidewall profiles when the process focus and exposure are optimized for critical dimension process control.
Another concern in integrated circuit and nanostructure manufacturing involves the deposition of a dielectric layer over metal conductors. If the slope of the sides of the metal conductors are essentially perpendicular or have negative slope due to undercutting of the metal layer during etching of the metal layer used to form the conductors, the dielectric layer might contain voids formed during deposition of the dielectric over the metal conductors, causing reliability problems because of moisture ingression in the voids causing corrosion to the metal layers. Further, the dielectric layer may not adhere to the metal layer sufficiently to avoid moisture ingression along the dielectric-metal interface.
It is therefore advantageous to have a gradually sloping under-layer so that the layer deposited on the under-layer smoothly and uniformly follows the contour of the under-layer. In one example, it is desirable to have an etched contact via opening with a gradual slope to assist with depositing an even metal film during the metal contact formation.
Generally, there are two known techniques to provide an under-layer with sloped sides. The first technique involves creating a protective layer along the sidewall of the layer being etched, thereby creating a tapered, non-vertical sidewall. The second technique involves forming a slope in the sidewall of a patterned photoresist layer used to mask the layer being etched, and then transferring the slope from the photoresist sidewall to the etched layer sidewall during a conventional etching step. There are multiple variants on the latter technique as will be discussed below.
The first technique mentioned above regarding the use of a protective layer to creating a taper to a dielectric or a metal layer is to form, during the etch, a protective polymeric layer on the sidewall of the material layer being etched. One example of this technique is disclosed in U.S. Pat. No. 4,919,748 for taper etching of an aluminum layer using a polymeric layer formed by adjusting the etch process parameters and gases during the etch. However, this technique utilizes a transient etch-resistant film on the layer being etched that might not create uniformly sloped aluminum sidewalls across a wafer and involves the etching of aluminum, not a dielectric. Further, the non-uniformity or variance of the taper angle is additive to the exposure process variations and might worsen critical dimension (CD) uniformity. Hence, the technique of using sloped photoresist sidewalls to create a sloped underlayer is generally preferred.
The second technique mentioned above is to create a sloped photoresist sidewall before etching of the underlying layer occurs. One approach to create the sloped resist profile is to “hard bake” the patterned resist, such as subjecting a novolac-based resist to temperatures between 120 and 130° C. using an oven bake, or a hotplate bake. At these temperatures, the resist softens and begins to flow at the edges of the patterns. Above this temperature range the resist hardens so much that the resist becomes too hard to be removed after use with reasonable effort, and, if baked at too high a temperature and for too long a time, the resist may begin to cure such that resist removal becomes extremely difficult. Oven temperature uniformity can be difficult to control across the oven, sometimes varying up to +/4° C. This variation across a wafer lot, and across multiple lots loaded together in the oven, generates a wide range of slope non-uniformity. A hotplate bake process provides better uniformity between wafers with temperature control ranging +/−0.5° C. or better. However, a hard bake process variation to the resist profile is additive to the variation due just to the exposure process.
Another approach to create a sloped photoresist profile is to defocus the exposure of the resist during patterning. This method limits the slope variation to just the exposure process, but large offsets can result in a loss in critical dimension control for a contact via opening defined by the sloped photoresist. For example, a 2.5 um resist photo process over a polyimide film, a 2 um square via reticle feature can result in a round via pattern with a sloped profile of about 80 degrees from vertical when the image is defocused during exposure at −1.5 um. It is also possible to get a resist sidewall angle of 77 degrees with a defocus of −3 um, but it has been found that this amount of defocus makes it difficult to control via opening dimensions at the bottom of a via. Additionally, focus control at the edge of the wafer can be difficult with some steppers. At the edges of the wafer, the laser focus algorithms in the stepper generally do not have enough data to calculate stepper field planarity and must average focus measurements from partial data or use data from adjacent stepper fields. The variation in focus at the edge of the wafer can generate inconsistent resist sloped profiles and can generate poor CD uniformity which increases when defocusing resist exposure is used to generate a sloped profile.
One additional approach to create a sloped photoresist profile is to use a dry-etch process to erode the edges of the resist as the chemical components of the etch chemically removes the underlying film layer. Since the etch rate is not uniform across the wafer, the resist is erroded non-uniformly during the etch. The resist non-uniformity is then added to the non-uniformity of the etch of the layer under the resist. Like the protective polymeric layer approach discussed above, the variation of this process on the sloped profile is also additive to the variation due to the exposure process and might worsen CD uniformity.
Unfortunately, none of the above sloped resist profile approaches result in a uniform and controllable tapered profile to via or other types of openings in dielectric material layers or on sidewalls of conductive layers. Thus, another approach is needed that allows for uniform, controllable sidewall profile angles for dielectric or conductive layers in integrated circuits or nanostructures, without significantly impacting CD uniformity across the wafer.